Ixia’s K2 40-Gigabit Ethernet (GE) Quad Small Form-factor Pluggable (QSFP+) SFF-8436-complaint test module is the world’s first-to-market layer 1 through 7 measurement and analysis test solution using a native QSFP+ MSA interface. The K2 QSFP+ load module is an essential tool for the development of 40GE network devices such as routers, switches, server network interface cards (NICs), converged network adapters (CNAs), and semiconductor communications devices.
K2 load modules measure and analyze the performance of IEEE 802.3ba-standard higher speed Ethernet (HSE) devices at line rate. The K2 interface is compatible with Ixia’s chassis and broad range of Ethernet interfaces, allowing real-world, full product testing in a single box. As part of Ixia’s K2 family of HSE products, the 40GE QSFP+ load module has the same feature set, test application, and automation capabilities as Ixia’s first-to-market 40GE and 100GE test modules with the CFP MSA interface.
HSE40GEQSFP1-01, 40GE QSFP+ Load Module
Ixia was an active participant in the HSE standardization effort and assisted in developing the new physical coding sublayer (PCS) lanes distribution methodology, a key enabler of the new HSE technology.
Ixia’s K2 load modules are valuable tools for developers who are integrating firmware and software into new electronics hardware, or integrating optical transceivers into their network devices and systems, especially unframed BERT test capabilities. Ixia’s K2 modules validate and benchmark the performance limits of these network devices by employing layer 1, 2 and 3 stress testing; virtual scalability testing; and negative testing. Ixia’s K2 load modules ensure that network devices interoperate with other manufacturers’ devices.
Key features
- Industry’s first 40GE IP test solution for layer 2 through 7
- 12 ports per XM12 chassis (10 rack mount units)
- Compatible with XM12 (941-0002) and XM12 High Performance chassis (941-0009)
- 2 ports per XM2 (941-0003) desktop chassis
- Industry’s first commercially-available PCS Lanes test system
- Checks compliance and performance against the IEEE 802.3ba with a full array of statistics and real-time error indicators
- Injects and tracks errors in lane markers, 64/66b payloads, and synchronization bits with controls for different configurations of error injections
- Complete standard-compliance testing for the PCS
- Unframed BERT support with individual PCS lanes BERT test and error injection over a wide range of PRBS patterns, including standard PMD support. A full set of BERT-related and bit error ratio (BER) statistics are available.
- Generates and analyses full 40GE line rate traffic
- Tracks and analyzes up to 1 million flows per port for:
- Real-time latency and delay variation
- Inter-arrival time
- Packet loss
- Data integrity
- Sequence checking
- Packet capture
- Tracks and analyzes up to 1 million flows per port for:
- Comprehensive layer 2-7 testing with integrated data plane and control plane traffic generation and analysis.
Specifications
| Feature | 40 Gigabit Ethernet |
|---|---|
| Load module | HSE40GEQSFP1-01 |
| Number of ports per module | 1 |
| Number of chassis slots per module | 1 |
| Maximum ports per chassis: | |
|
12 12 2 |
| Supported transceivers/cables | QSFP+ SFF-8436 for copper and optical cables |
| Per-port CPU speed and memory | 1 GHz / 2GB |
| Per-port capture buffer | 700MB |
| Interface protocol | 40GE per IEEE 802.3ba standard, 40GBASE-R LAN |
| Layer 2/3 routing protocol emulation | Yes |
| Layer 4-7 application traffic testing | No |
| Number of transmit flows per port (sequential values) | Billions |
| Number of transmit flows per port (non-sequential values ) | 1 million |
| Number of trackable receive flows | 1 million |
| Number of stream definitions per port |
512 In packet stream (sequential) or advanced stream (interleaved) mode, each stream definition can generate millions of unique traffic flows. |
| Table UDF entries |
1 million Comprehensive packet editing function for emulating large numbers of sophisticated flows. Entries of up to 256 bytes, using lists of values can be specified and placed at designated offsets within a stream. Each list consists of an offset, a size, and a list of values in a table format. |
| Packet flow statistics | Track over 1 million flows |
| Transmit engine | Wire-speed packet generation with timestamps, sequence numbers, data integrity signature, and packet group signatures |
| Receive engine | Wire-speed packet filtering, capturing, real-time latency and inter-arrival time for each packet group, data integrity, and sequence checking |
| User defined field features | Fixed, increment or decrement by user-defined step, value lists, range lists, cascade, random, and chained |
| Filters | 48-bit source/destination address, 2×128-bit user-definable pattern and offset, frame length range, CRC error, data integrity error, sequence checking error (small, big, reverse) |
| Data field per stream | Fixed, increment or decrement by user-defined step, value lists, range lists, cascade, random, and chained |
| Statistics and rates (counter size: 64 bits) | Link state, line speed, frames sent, valid frames received, bytes sent/received, fragments, undersize, oversize, CRC errors, VLAN tagged frames, 6 user-defined stats, capture trigger (UDS 3), capture filter (UDS 4), user-defined stat 5, user-defined stat 6, 8 QoS counters, data integrity frames, data integrity errors, sequence checking frames, sequence checking errors, ARP, and ping requests and replies |
| Error generation | CRC (good/bad/none), undersize, oversize |
| Latency measurement resolution | 2.5 nanoseconds and is compatible with all of Ixia’s 10GbE, 1GbE fiber, and 10/100/1000Mbps Ethernet, ATM, and packet over SONET load modules |
| Latency self-calibration | Ability to calibrate and remove inherent latency from any MSA-compliant 40GE CFP transceiver |
| MDIO | MDIO support is provided for CFP MSA compliant transceivers |
| Transmit line clock adjustment | Ability to adjust the parts per million (ppm) line frequency over a range of -100 to +100 ppm |
| Clock IN/OUT | TThe load module provides two pairs of female SMA coaxial connectors – one for clock input and one for clock output – to allow the device under test (DUT) to frequency-lock with the load module interface. When running off an external clock source, the clock input signal must meet the requirements listed in the current Ixia Hardware and Reference Manual. |
| Layer 1 BERT capability | The load module supports the following BERT features on 40Gb/s speeds:
|
| 40GE physical coding sublayer (PCS) test features: | IEEE 802.3ba-compliant PCS transmit and receive side test capabilities |
|
Supports all combinations of PCS lane mapping: Default, Increment, Decrement, Random, and Custom |
|
User selectable from zero up to 3 microseconds of PCS lane skew insertion on the transmit side |
|
User-selectable ability to inject errors into the PCS Lane Marker and simultaneously into PCS Lane Marker and Payload fields. This includes the ability to inject sync bit errors into the Lane Marker and Payload. User can control the PCS lane, number or errors, and period count; and manage the repetition of the injected errors. |
|
PCS Sync Header and Lane Marker Lock, Lane Marker mapping, Relative lane deskew up to 52 microseconds, Sync Header and PCS Lane Marker Error counters, indicators for Loss of Synch Header and Lane Marker, BIP8 errors |
| IPv4, IPv6, UDP, TCP checksum | Hardware checksum generation and verification |
| Frame length controls | Fixed, random, weighted random, or increment by user-defined step, random, weighted random |
| Preamble view | Allows the user to select to view and edit the preamble contents |
| Link fault signaling | Generate local and remote faults with controls for the number of faults and order of faults, plus the ability to select the option to have the transmit port ignore link faults from a remote link partner |
| Operating temperature range | 41°F to 95°F (5°C to 35°C), ambient air1 |
Application support
|
ATTENTION PLEASE!
IXIA CLIENT SOFTWARE: The software provided on all Ixia items is the server software only. The server software has ixserver and ixplorer as the only desktop applications. The server application licensed features are accessed through various Ixia client applications that interact with the chassis server.
You can download the Ixia client applications if you have online access with Ixia. These client applications are typically free from Ixia but you will need an Ixia logon account. We offer a selection of these applications to our customers at no charge but the selection is incomplete. We do not sell these with the servers as a package. Client application needs are the buyers responsibility, we do not guarantee that we will have all your needs though we will try to assist you if we can. We only guarantee the server applications as itemized in the listings.
In a single user environment you can set the client side GUI interface on a external PC or you can set them up on an application server when using a chassis in a multi-user environment to access and configure all the sub-license features included in a listing. Multiple chassis can be accessed in the client applications environment which allows you to use the licensed features of several chassis all at once in one interface.
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QUALITY CONTROL
Electronics in general, where possible items are tested. The value of an item greatly contributes to the amount or effort put into testing. It just isn’t possible to test many low value items due to the time required and the expenses associated with it. Items that are not specifically tested in detail are visually inspected and reviewed for their operational status. When purchasing recycled items, it is reasonable to have varying quality and occasional failures. Just remember you are covered with a money back guarantee on most items. We want you to be happy above all other considerations.
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Ixia’s K2 40-Gigabit Ethernet (GE) Quad Small Form-factor Pluggable (QSFP+) SFF-8436-complaint test module is the world’s first-to-market layer 1 through 7 measurement and analysis test solution using a native QSFP+ MSA interface. The K2 QSFP+ load module is an essential tool for the development of 40GE network devices such as routers, switches, server network interface cards (NICs), converged network adapters (CNAs), and semiconductor communications devices.
K2 load modules measure and analyze the performance of IEEE 802.3ba-standard higher speed Ethernet (HSE) devices at line rate. The K2 interface is compatible with Ixia’s chassis and broad range of Ethernet interfaces, allowing real-world, full product testing in a single box. As part of Ixia’s K2 family of HSE products, the 40GE QSFP+ load module has the same feature set, test application, and automation capabilities as Ixia’s first-to-market 40GE and 100GE test modules with the CFP MSA interface.
HSE40GEQSFP1-01, 40GE QSFP+ Load Module
Ixia was an active participant in the HSE standardization effort and assisted in developing the new physical coding sublayer (PCS) lanes distribution methodology, a key enabler of the new HSE technology.
Ixia’s K2 load modules are valuable tools for developers who are integrating firmware and software into new electronics hardware, or integrating optical transceivers into their network devices and systems, especially unframed BERT test capabilities. Ixia’s K2 modules validate and benchmark the performance limits of these network devices by employing layer 1, 2 and 3 stress testing; virtual scalability testing; and negative testing. Ixia’s K2 load modules ensure that network devices interoperate with other manufacturers’ devices.
Key features
- Industry’s first 40GE IP test solution for layer 2 through 7
- 12 ports per XM12 chassis (10 rack mount units)
- Compatible with XM12 (941-0002) and XM12 High Performance chassis (941-0009)
- 2 ports per XM2 (941-0003) desktop chassis
- Industry’s first commercially-available PCS Lanes test system
- Checks compliance and performance against the IEEE 802.3ba with a full array of statistics and real-time error indicators
- Injects and tracks errors in lane markers, 64/66b payloads, and synchronization bits with controls for different configurations of error injections
- Complete standard-compliance testing for the PCS
- Unframed BERT support with individual PCS lanes BERT test and error injection over a wide range of PRBS patterns, including standard PMD support. A full set of BERT-related and bit error ratio (BER) statistics are available.
- Generates and analyses full 40GE line rate traffic
- Tracks and analyzes up to 1 million flows per port for:
- Real-time latency and delay variation
- Inter-arrival time
- Packet loss
- Data integrity
- Sequence checking
- Packet capture
- Tracks and analyzes up to 1 million flows per port for:
- Comprehensive layer 2-7 testing with integrated data plane and control plane traffic generation and analysis.
Specifications
| Feature | 40 Gigabit Ethernet |
|---|---|
| Load module | HSE40GEQSFP1-01 |
| Number of ports per module | 1 |
| Number of chassis slots per module | 1 |
| Maximum ports per chassis: | |
|
12 12 2 |
| Supported transceivers/cables | QSFP+ SFF-8436 for copper and optical cables |
| Per-port CPU speed and memory | 1 GHz / 2GB |
| Per-port capture buffer | 700MB |
| Interface protocol | 40GE per IEEE 802.3ba standard, 40GBASE-R LAN |
| Layer 2/3 routing protocol emulation | Yes |
| Layer 4-7 application traffic testing | No |
| Number of transmit flows per port (sequential values) | Billions |
| Number of transmit flows per port (non-sequential values ) | 1 million |
| Number of trackable receive flows | 1 million |
| Number of stream definitions per port |
512 In packet stream (sequential) or advanced stream (interleaved) mode, each stream definition can generate millions of unique traffic flows. |
| Table UDF entries |
1 million Comprehensive packet editing function for emulating large numbers of sophisticated flows. Entries of up to 256 bytes, using lists of values can be specified and placed at designated offsets within a stream. Each list consists of an offset, a size, and a list of values in a table format. |
| Packet flow statistics | Track over 1 million flows |
| Transmit engine | Wire-speed packet generation with timestamps, sequence numbers, data integrity signature, and packet group signatures |
| Receive engine | Wire-speed packet filtering, capturing, real-time latency and inter-arrival time for each packet group, data integrity, and sequence checking |
| User defined field features | Fixed, increment or decrement by user-defined step, value lists, range lists, cascade, random, and chained |
| Filters | 48-bit source/destination address, 2×128-bit user-definable pattern and offset, frame length range, CRC error, data integrity error, sequence checking error (small, big, reverse) |
| Data field per stream | Fixed, increment or decrement by user-defined step, value lists, range lists, cascade, random, and chained |
| Statistics and rates (counter size: 64 bits) | Link state, line speed, frames sent, valid frames received, bytes sent/received, fragments, undersize, oversize, CRC errors, VLAN tagged frames, 6 user-defined stats, capture trigger (UDS 3), capture filter (UDS 4), user-defined stat 5, user-defined stat 6, 8 QoS counters, data integrity frames, data integrity errors, sequence checking frames, sequence checking errors, ARP, and ping requests and replies |
| Error generation | CRC (good/bad/none), undersize, oversize |
| Latency measurement resolution | 2.5 nanoseconds and is compatible with all of Ixia’s 10GbE, 1GbE fiber, and 10/100/1000Mbps Ethernet, ATM, and packet over SONET load modules |
| Latency self-calibration | Ability to calibrate and remove inherent latency from any MSA-compliant 40GE CFP transceiver |
| MDIO | MDIO support is provided for CFP MSA compliant transceivers |
| Transmit line clock adjustment | Ability to adjust the parts per million (ppm) line frequency over a range of -100 to +100 ppm |
| Clock IN/OUT | TThe load module provides two pairs of female SMA coaxial connectors – one for clock input and one for clock output – to allow the device under test (DUT) to frequency-lock with the load module interface. When running off an external clock source, the clock input signal must meet the requirements listed in the current Ixia Hardware and Reference Manual. |
| Layer 1 BERT capability | The load module supports the following BERT features on 40Gb/s speeds:
|
| 40GE physical coding sublayer (PCS) test features: | IEEE 802.3ba-compliant PCS transmit and receive side test capabilities |
|
Supports all combinations of PCS lane mapping: Default, Increment, Decrement, Random, and Custom |
|
User selectable from zero up to 3 microseconds of PCS lane skew insertion on the transmit side |
|
User-selectable ability to inject errors into the PCS Lane Marker and simultaneously into PCS Lane Marker and Payload fields. This includes the ability to inject sync bit errors into the Lane Marker and Payload. User can control the PCS lane, number or errors, and period count; and manage the repetition of the injected errors. |
|
PCS Sync Header and Lane Marker Lock, Lane Marker mapping, Relative lane deskew up to 52 microseconds, Sync Header and PCS Lane Marker Error counters, indicators for Loss of Synch Header and Lane Marker, BIP8 errors |
| IPv4, IPv6, UDP, TCP checksum | Hardware checksum generation and verification |
| Frame length controls | Fixed, random, weighted random, or increment by user-defined step, random, weighted random |
| Preamble view | Allows the user to select to view and edit the preamble contents |
| Link fault signaling | Generate local and remote faults with controls for the number of faults and order of faults, plus the ability to select the option to have the transmit port ignore link faults from a remote link partner |
| Operating temperature range | 41°F to 95°F (5°C to 35°C), ambient air1 |
Application support
|
| Weight | 18 lbs |
|---|---|
| Dimensions | 20 × 16 × 6 in |
| MODEL | HSE40GEQSFP1-01 |
| MPN | HSE40GEQSFP1-01 |
| Brand | Ixia |
Brand
Ixia
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